Many consumer electronic products help to satisfy consumer need of basic communications and entertainment services. Such consumer electronic products include televisions, digital cameras, cellular telephones, media content players, etc. Components that play important roles in the operation of these technologies include processors and data storage devices. Data storage devices include RAM, ROM, flash memory products, etc.
An important parameter of data storage devices is memory cell density. It should be appreciated that memory cell density of data storage devices such as memory arrays is important because data storage capacity per unit area of the memory array is directly related thereto. There are many approaches to increasing the memory cell density of memory arrays. One approach involves reducing the channel length between the source and the drain of respective transistors associated with respective memory cells in a memory array. This allows the size of each memory cell to be reduced which in turn facilitates the provision of denser memory arrays. Another approach to increasing memory cell density is embodied in a commercially available flash memory product called MirrorBit™ Technology from Spansion, located in Sunnyvale, Calif.
In flash memory arrays that use MirrorBit technology, a MirrorBit cell is employed that effectively doubles the intrinsic density of the flash memory array by storing two physically distinct bits on opposite sides of a memory cell. Each bit that is stored within a cell serves as a binary unit of data (either a logic one or zero) that is mapped directly to the memory array. The MirrorBit cell includes two source/drain regions formed in a silicon substrate. A storage element, that includes a first planer oxide layer, a nitride layer, and a second oxide layer, is formed on the silicon substrate. A polysilicon gate is then formed over the storage element. For more details on MirrorBit technology, see U.S. Pat. Nos. 6,861,307, 6,917,068, 6,639,271, 6,215,702 and 2004/0021172, each of which are incorporated herein by reference.
An exemplary MirrorBit™ memory device includes a semiconductor substrate with spaced apart source and a drain regions (both typically having N-type conductivity) formed in the bulk of the substrate. An oxide-nitride-oxide (ONO) layered stack is formed on the top surface of the substrate between the source and drain regions. A gate electrode, which typically comprises an N or N+ polysilicon layer, is formed over the ONO stack. The ONO stack includes a first or bottom dielectric layer (often referred to as a bottom tunnel oxide), a charge storing nitride layer, and a second or top dielectric layer of oxide.
Programming of such a MirrorBit™ cell can be accomplished, for example, by hot electron injection. Hot electron injection involves applying appropriate voltage potentials to each of the gate, the source, and the drain of the cell for a specified duration until the charge storing layer accumulates charge. Such a process is disclosed in U.S. Pat. No. 6,215,702, which is incorporated herein by reference in its entirety.
Erasure of a MirrorBit™ cell can be accomplished using, for example, the conventional technique of “hot hole injection” (sometimes referred to as band-to-band (BTB) hot hole injection). In hot hole injection a gate voltage of 4.0 to 8.0 volts is applied along with a drain voltage on the order of 4.0-6.0 volts, while the source is floated or grounded to erase one of the memory cells (typically the normal bit). Conversely, the complementary bit cell is erased by floating the drain and applying the appropriate voltage to the source and the gate. With such erase conditions, a BTB tunnel current is created under the gate. Holes are generated under these conditions and accelerate from the N-type drain region into the P-type substrate. The generated holes are accelerated in the electrical field created near the P-N drain/body junction. Some of the accelerated holes surmount the oxide to silicon interface between the substrate and the bottom oxide and are injected into the nitride layer to displace electrons (e.g., by recombination) and erase the cell.
Another erase mechanism is channel erase, also commonly referred to as a Fowler-Nordheim (FN) erase operation. Typically, in conventional MirrorBit™—type memory cells, the top and bottom oxides have the same dielectric constant, resulting in the vertical fields during the erase being the same across both the top and bottom oxides. Therefore, during an FN channel erase, electrons are pushed out from the charge storing layer to the substrate. At the same time, more electrons flow from the N gate through the top oxide and get trapped in the charge storing layer. Therefore, while there is a net current from the control gate to the substrate, charge is not erased effectively from the charge storing layer.
Problems with the above discussed memory types can include but are not limited to bit line punch through, channel hot electron injection (CHEI), complimentary bit disturb and transient bit disturb. These issues which can be aggravated by attempts to scale devices to smaller dimensions hamper efforts to further increase the density of flash memory devices.
Punch through occurs when diffusion associated with the source and drain regions of a transistor overlap. When this occurs a transistor can remain on even when a voltage intended to turn it off is applied to its gate. Punch through can be a potential problem in transistors such as those discussed above because the source and drain regions of such transistors are typically fabricated relatively closely together. As the pitch of memory cells becomes smaller and smaller with advances in semiconductor fabrication technology, punch through is likely to become an even more significant issue.
Channel hot electron injection (CHEI) occurs when charge that is associated with bits that are stored on opposite sides of a memory cell overlap. When this occurs dual bit ambiguity can be caused from channel hot electron injection (CHEI) program distribution and lateral charge diffusion as gate length is scaled down. The inability to distinguish bits during such a condition can result in erroneous readings.
Complimentary bit disturb occurs when the programming of one bit in a mirror bit memory cell causes electrons or holes to be injected into the charge storage space of a complimentary bit. When this occurs the programmed state of the complimentary bit can be affected which can cause erroneous readings of the bit. Complimentary bit disturb can be a problem in transistors such as those discussed above because the charge storage space of the bits in such transistors are closely located.
Transient bit disturb occurs when the programming of one bit in a mirror bit memory cell causes electrons or holes to be injected into the charge storage space of an adjacent cell. When this occurs the programmed state of the adjacent cell can be affected which can cause erroneous readings. Transient bit disturb can be a potential problem in mirror bit memory arrays such as those discussed above because the memory cells in such memory arrays are typically fabricated relatively closely together.
Additional issues associated with the above discussed Mirror Bit™ device are related to structural and functional features of the device. For example, it can be difficult to reduce the size or pitch of the cell because the storage element of the above-mentioned flash memory cell is planar (the oxide, nitride and oxide layers are all horizontal layers formed one on top of the other on the silicon substrate). Moreover, as it regards the above discussed erasure of a Mirror Bit™ cell by hot hole injection, because these hot holes bombard the interface between the substrate and the bottom tunnel oxide, the interface as well as the bottom tunnel oxide can be damaged causing undesirable interface states and degraded reliability over program/erase cycling.
As can be seen from the above discussion, conventional approaches to increasing memory cell density are inadequate. These approaches can precipitate undesirable consequences that negatively affect device function.